文献类型： 会议论文

第一作者： Steven Wu

作者： Steven Wu ¹ ; Sho-Shen Lee ¹ ; Chun-Chi Yu ¹ ; Benjamin Lin ¹ ; Cheng Bai Xu ² ; Yasuhiro Suzuki ² ; Stewart Robertson ² ; Tsutomu Tanaka ² ; I-Yuan Wan ² ;

作者机构： 1.United Microelectronics Corp

2.Rohm and Haas Electronic Materials

关键词： back-end metal trench;forbidden pitch;MEF;proximity;line edge roughness

会议名称： Advances in resist technology and processing XXIII

主办单位：

页码： 615334-1-615334-14

摘要： A combination of simulation, resist modification and process optimization were used to develop production worthy dry 193nm lithography processes, suitable for the metal trench layers of 65nm node logic devices. The important performance characteristics of a back-end metal trench layer are through-pitch proximity bias, lithographic latitude and ultimate resolution. Simulation results suggested that a moderate annular illumination setting balances proximity bias against resolution at the forbidden pitch, yielding a good overall through-pitch common process window. Resist material optimization through resin, PAG (photo-acid generator) and base quencher modification improves proximity bias and results in excellent lithographic performances of good LER (line edge roughness), low MEF (Mask Error Factor) and wider process latitude. To investigate extendibility to 45nm node applications, the immersion compatibility of the optimized resist with several top coats are reported.

分类号： N5